Initial commit of de10-nano recipes

Please note that this is purely for development.  Only superficial
efforts have been made to resolve security concerns, and it should
be noted that the board ships with an EMPTY ROOT PASSWORD and support
for root login via ssh.  This allows passwordless access to the board
via ssh.

recipes-bsp/u-boot:
Contains the uboot 2017.03rc2 recipe and patches to support the
de10-nano board

recipes-connectivity/avahi:
bbappend to remove unwanted packages

recipes-connectivity/bluez:
bbappend to add --compat to the bluetooth service to support legacy
SDP APIs

recipes-connectivity/openssh:
bbappend to add a custom sshd_config

recipes-core/base-files:
bbappend to customize fstab and inputrc

recipes-core/imagemagick:
bbappend to change build configuration for the de10-nano board

recipes-core/packagegroups:
bbappend to remove an unwanted package

recipes-core/webkit:
bbappend to remove support for opengl

recipes-demo:
Various demo applications

recipes-devtools:
MRAA and UPM recipes

recipes-images/angstrom/de10-nano-image.bb:
DE10-Nano image definition

recipes-kernel/de10-nano-linux-firmware:
FPGA related firmware required for fpga configuration and devicetree
overlay support

recipes-kernel/linux:
bbappend to customize configuration of linux kernel as well as patch
in the de10-nano devicetree

recipes-misc:
various initialization and systemd scripts

recipes-qt/qt5:
bbappend to modify qt build options

recipes-support/neon:
bbappend to remove unwanted package

recipes-support/upower:
bbappend to remove unwanted package

recipes-webserver:
webserver configuration and webcontent for board hostedweb portal

recipes-xfce/thunar-volman:
bbappend to remove unwanted package

recipes-xfce/xfce-pointers:
add configuration so that xfce does not use the adxl input as a mouse

recipes-xfce/xfce4-settings:
bbappend to remove unwanted package

Signed-off-by: Westergreen, Dalon <dalon.westergreen@intel.com>

6 files changed, 2612 insertions, 0 deletions

diff --git a/recipes-demo/de10-nano-fftdriver-mod/.atlas-soc-fftdriver-mod_0.1.bb.swp b/recipes-demo/de10-nano-fftdriver-mod/.atlas-soc-fftdriver-mod_0.1.bb.swp
new file mode 100644
index 0000000..cfa2644
--- /dev/null
+++ b/recipes-demo/de10-nano-fftdriver-mod/.atlas-soc-fftdriver-mod_0.1.bb.swp
diff --git a/recipes-demo/de10-nano-fftdriver-mod/de10-nano-fftdriver-mod.bb b/recipes-demo/de10-nano-fftdriver-mod/de10-nano-fftdriver-mod.bb
new file mode 100644
index 0000000..2cd0e76
--- /dev/null
+++ b/recipes-demo/de10-nano-fftdriver-mod/de10-nano-fftdriver-mod.bb
@@ -0,0 +1,23 @@
+SUMMARY = "Example Driver for DE10-Nano FPGA based FFT"
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = "file://COPYING;md5=12f884d2ae1ff87c09e5b7ccc2c4ca7e"
+SECTION = "DE10-Nano"
+
+inherit module
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+PR = "r0"
+PV = "1.0"
+PV_append = "+${PR}"
+
+SRC_URI = "file://Makefile \
+           file://COPYING \
+           file://fft_driver.c \
+           file://fft_driver.h \
+          "
+
+S = "${WORKDIR}"
+
+# The inherit of module.bbclass will automatically name module packages with
+# "kernel-module-" prefix as required by the oe-core build environment.
diff --git a/recipes-demo/de10-nano-fftdriver-mod/files/COPYING b/recipes-demo/de10-nano-fftdriver-mod/files/COPYING
new file mode 100644
index 0000000..6d45519
--- /dev/null
+++ b/recipes-demo/de10-nano-fftdriver-mod/files/COPYING
@@ -0,0 +1,340 @@
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+                       51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
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+  If you develop a new program, and you want it to be of the greatest
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+    Copyright (C) <year>  <name of author>
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+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
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+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
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+    Gnomovision version 69, Copyright (C) year name of author
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+    This is free software, and you are welcome to redistribute it
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+The hypothetical commands `show w' and `show c' should show the appropriate
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+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.
diff --git a/recipes-demo/de10-nano-fftdriver-mod/files/Makefile b/recipes-demo/de10-nano-fftdriver-mod/files/Makefile
new file mode 100644
index 0000000..024f913
--- /dev/null
+++ b/recipes-demo/de10-nano-fftdriver-mod/files/Makefile
@@ -0,0 +1,14 @@
+obj-m := fft_driver.o
+
+SRC := $(shell pwd)
+
+all:
+	$(MAKE) -C $(KERNEL_SRC) M=$(SRC)
+
+modules_install:
+	$(MAKE) -C $(KERNEL_SRC) M=$(SRC) modules_install
+
+clean:
+	rm -f *.o *~ core .depend .*.cmd *.ko *.mod.c
+	rm -f Module.markers Module.symvers modules.order
+	rm -rf .tmp_versions Modules.symvers
diff --git a/recipes-demo/de10-nano-fftdriver-mod/files/fft_driver.c b/recipes-demo/de10-nano-fftdriver-mod/files/fft_driver.c
new file mode 100644
index 0000000..9ef1cb0
--- /dev/null
+++ b/recipes-demo/de10-nano-fftdriver-mod/files/fft_driver.c
@@ -0,0 +1,2159 @@
+/*
+ * Copyright (C) 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/miscdevice.h>
+#include <linux/mm.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include "fft_driver.h"
+
+/* globals */
+static struct semaphore g_dev_probe_sem;
+static int g_platform_probe_flag;
+
+/* structures */
+struct fft_samples_struct {
+	short i;
+	short r;
+};
+
+struct raw_samples_struct {
+	long r;
+	long i;
+};
+
+/* fft_dev structure and storage allocation */
+struct fft_dev {
+	struct semaphore sem;
+	uint32_t phys_fft_st_adapter;
+	uint32_t size_fft_st_adapter;
+	void *ioremap_fft_st_adapter;
+	uint32_t phys_fft_data_ram;
+	uint32_t size_fft_data_ram;
+	void *ioremap_fft_data_ram;
+	uint32_t phys_sgdma_from_fft_descriptor;
+	uint32_t size_sgdma_from_fft_descriptor;
+	void *ioremap_sgdma_from_fft_descriptor;
+	uint32_t phys_sgdma_from_fft_csr;
+	uint32_t size_sgdma_from_fft_csr;
+	void *ioremap_sgdma_from_fft_csr;
+	uint32_t phys_sgdma_to_fft_descriptor;
+	uint32_t size_sgdma_to_fft_descriptor;
+	void *ioremap_sgdma_to_fft_descriptor;
+	uint32_t phys_sgdma_to_fft_csr;
+	uint32_t size_sgdma_to_fft_csr;
+	void *ioremap_sgdma_to_fft_csr;
+	uint32_t phys_sgdma_from_ram_descriptor;
+	uint32_t size_sgdma_from_ram_descriptor;
+	void *ioremap_sgdma_from_ram_descriptor;
+	uint32_t phys_sgdma_from_ram_csr;
+	uint32_t size_sgdma_from_ram_csr;
+	void *ioremap_sgdma_from_ram_csr;
+	int fft_open_for_read;
+	int fft_open_for_write;
+	int fft256_open_for_read;
+	int fft256_open_for_write;
+	int fftdma_open_for_read;
+	int fftdma_open_for_write;
+	int fft256dma_open_for_read;
+	int fft256dma_open_for_write;
+	int fft256stream_open_for_read;
+	int fft256stream_open_for_write;
+	int raw256stream_open_for_read;
+	int raw256stream_open_for_write;
+	uint32_t fft256_buffer_read_index;
+	uint32_t fft256_buffer_write_index;
+	uint32_t fft256_buffer_inflight_count;
+	void *dma_buffer;
+	dma_addr_t dma_handle;
+};
+
+static struct fft_dev the_fft_dev = {
+	/*
+	   .sem = initialize this at runtime before it is needed
+	 */
+};
+
+/* misc device - raw256stream_dev */
+static ssize_t raw256stream_dev_write(struct file *fp,
+				      const char __user *user_buffer,
+				      size_t count, loff_t *offset)
+{
+	struct fft_dev *dev = fp->private_data;
+
+	if (down_interruptible(&dev->sem))
+		return -ERESTARTSYS;
+
+	if (count > (64 * 1024)) {
+		up(&dev->sem);
+		return -EINVAL;
+	}
+
+	/* move the input data from the user buffer into the fft data buffer */
+	if (copy_from_user
+	    (dev->ioremap_fft_data_ram + DMA_DATA_OFFSET, user_buffer, count)) {
+		up(&dev->sem);
+		pr_info("raw256stream_dev_write copy_from_user exit\n");
+		return -EFAULT;
+	}
+
+	up(&dev->sem);
+	return count;
+}
+
+static ssize_t raw256stream_dev_read(struct file *fp, char __user *user_buffer,
+				     size_t count, loff_t *offset)
+{
+	struct fft_dev *dev = fp->private_data;
+	uint32_t dma_status;
+	uint32_t dma_desc_fill_level;
+	int this_count = 256;
+	int write_block_count = 0;
+	int read_block_count = 0;
+	int read_count = 0;
+	int next_fft256_buffer_offset;
+
+	if (down_interruptible(&dev->sem))
+		return -ERESTARTSYS;
+
+	/* validate count request */
+	if (count & ((this_count * 8) - 1)) {
+		up(&dev->sem);
+		return -EINVAL;
+	}
+
+	if (count > 0)
+		read_block_count = count / (this_count * 8);
+	else
+		read_block_count = 0;
+
+	write_block_count = read_block_count;
+
+	while ((write_block_count > 0) || (read_block_count > 0)) {
+		while (write_block_count > 0) {
+			if (dev->fft256_buffer_inflight_count >= 32)
+				break;
+
+			next_fft256_buffer_offset =
+			    dev->fft256_buffer_write_index * this_count * 8;
+
+			/* start the read from RAM DMA */
+			iowrite32(DMA_RAM_DATA_ADDR,
+				  dev->ioremap_sgdma_from_ram_descriptor +
+				  DESC_READ_ADDRESS_REG);
+			iowrite32(dev->dma_handle + next_fft256_buffer_offset,
+				  dev->ioremap_sgdma_from_ram_descriptor +
+				  DESC_WRITE_ADDRESS_REG);
+			iowrite32(this_count * 8,
+				  dev->ioremap_sgdma_from_ram_descriptor +
+				  DESC_LENGTH_REG);
+			iowrite32(START_DMA_FROM_FFT_MASK,
+				  dev->ioremap_sgdma_from_ram_descriptor +
+				  DESC_CONTROL_REG);
+
+			/* maintain counters and pointers */
+			write_block_count--;
+			dev->fft256_buffer_inflight_count++;
+			dev->fft256_buffer_write_index++;
+			if (dev->fft256_buffer_write_index >= 32)
+				dev->fft256_buffer_write_index = 0;
+		}
+
+		while (read_block_count > 0) {
+			if (dev->fft256_buffer_inflight_count == 0)
+				break;
+
+			if (dev->fft256_buffer_inflight_count >= 2) {
+				/* wait for at least two descriptors to be used
+				*/
+				do {
+					dma_desc_fill_level =
+					    ioread32(dev->
+						     ioremap_sgdma_from_ram_csr
+						     +
+						 CSR_DESCRIPTOR_FILL_LEVEL_REG);
+					dma_desc_fill_level &=
+					CSR_WRITE_FILL_LEVEL_MASK;
+					dma_desc_fill_level >>=
+				      CSR_WRITE_FILL_LEVEL_OFFSET;
+				} while (dma_desc_fill_level >
+					 (dev->fft256_buffer_inflight_count -
+					  2));
+			} else {
+				/* wait for all descriptors to be used */
+				do {
+					dma_desc_fill_level =
+					    ioread32(dev->
+						     ioremap_sgdma_from_ram_csr
+						     +
+						 CSR_DESCRIPTOR_FILL_LEVEL_REG);
+					dma_desc_fill_level &=
+					CSR_WRITE_FILL_LEVEL_MASK;
+					dma_desc_fill_level >>=
+				      CSR_WRITE_FILL_LEVEL_OFFSET;
+				} while (dma_desc_fill_level > 0);
+
+				/* wait for read from FFT DMA to complete */
+				do {
+					dma_status =
+					    ioread32(dev->
+						     ioremap_sgdma_from_ram_csr
+						     + CSR_STATUS_REG);
+				} while ((dma_status &
+					  CSR_BUSY_MASK) != 0);
+			}
+
+			/* move the results buffer into the user buffer */
+			next_fft256_buffer_offset =
+			    dev->fft256_buffer_read_index * this_count * 8;
+			if (copy_to_user
+			    (user_buffer,
+			     dev->dma_buffer + next_fft256_buffer_offset,
+			     this_count * 8)) {
+				up(&dev->sem);
+				pr_info
+				  ("raw256stream_dev_read copy_to_user exit\n");
+				return -EFAULT;
+			}
+
+			/* maintain counters and pointers */
+			user_buffer += this_count * 8;
+			read_count += this_count * 8;
+			read_block_count--;
+			dev->fft256_buffer_inflight_count--;
+			dev->fft256_buffer_read_index++;
+			if (dev->fft256_buffer_read_index >= 32)
+				dev->fft256_buffer_read_index = 0;
+		}
+	}
+
+	up(&dev->sem);
+	return read_count;
+}
+
+static int raw256stream_dev_open(struct inode *ip, struct file *fp)
+{
+	struct fft_dev *dev = &the_fft_dev;
+	int ret_val;
+	uint32_t access_mode;
+
+	if (down_interruptible(&dev->sem))
+		return -ERESTARTSYS;
+
+	ret_val = -EBUSY;
+	if ((dev->fft256stream_open_for_read != 0) ||
+	    (dev->fft256stream_open_for_write != 0) ||
+	    (dev->fft_open_for_read != 0) ||
+	    (dev->fft_open_for_write != 0) ||
+	    (dev->fftdma_open_for_read != 0) ||
+	    (dev->fftdma_open_for_write != 0) ||
+	    (dev->fft256_open_for_read != 0) ||
+	    (dev->fft256_open_for_write != 0))
+		goto do_exit;
+
+	access_mode = fp->f_flags & O_ACCMODE;
+	switch (access_mode) {
+	case (O_RDONLY):
+		if (dev->raw256stream_open_for_read != 0)
+			goto do_exit;
+		dev->raw256stream_open_for_read = 1;
+		break;
+	case (O_WRONLY):
+		if (dev->raw256stream_open_for_write != 0)
+			goto do_exit;
+		dev->raw256stream_open_for_write = 1;
+		break;
+	case (O_RDWR):
+		if (dev->raw256stream_open_for_read != 0)
+			goto do_exit;
+		if (dev->raw256stream_open_for_write != 0)
+			goto do_exit;
+		dev->raw256stream_open_for_read = 1;
+		dev->raw256stream_open_for_write = 1;
+		break;
+	default:
+		ret_val = -EINVAL;
+		goto do_exit;
+	}
+
+	ret_val = 0;
+	fp->private_data = dev;
+
+do_exit:
+	up(&dev->sem);
+	return ret_val;
+}
+
+static int raw256stream_dev_release(struct inode *ip, struct file *fp)
+{
+	struct fft_dev *dev = fp->private_data;
+	int ret_val;
+	uint32_t access_mode;
+
+	if (down_interruptible(&dev->sem))
+		return -ERESTARTSYS;
+
+	ret_val = 0;
+
+	access_mode = fp->f_flags & O_ACCMODE;
+	switch (access_mode) {
+	case (O_RDONLY):
+		dev->raw256stream_open_for_read = 0;
+		break;
+	case (O_WRONLY):
+		dev->raw256stream_open_for_write = 0;
+		break;
+	case (O_RDWR):
+		dev->raw256stream_open_for_read = 0;
+		dev->raw256stream_open_for_write = 0;
+		break;
+	default:
+		ret_val = -EINVAL;
+		goto do_exit;
+	}
+
+do_exit:
+	up(&dev->sem);
+	return ret_val;
+}
+
+static const struct file_operations raw256stream_dev_fops = {
+	.owner = THIS_MODULE,
+	.open = raw256stream_dev_open,
+	.release = raw256stream_dev_release,
+	.read = raw256stream_dev_read,
+	.write = raw256stream_dev_write,
+};
+
+static struct miscdevice raw256stream_dev_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "raw256stream",
+	.fops = &raw256stream_dev_fops,
+};
+
+/* misc device - fft256stream_dev */
+static ssize_t fft256stream_dev_write(struct file *fp,
+				      const char __user *user_buffer,
+				      size_t count, loff_t *offset)
+{
+	struct fft_dev *dev = fp->private_data;
+
+	if (down_interruptible(&dev->sem))
+		return -ERESTARTSYS;
+
+	if (count > (64 * 1024)) {
+		up(&dev->sem);
+		return -EINVAL;
+	}
+
+	/* move the input data from the user buffer into the fft data buffer */
+	if (copy_from_user
+	    (dev->ioremap_fft_data_ram + DMA_DATA_OFFSET, user_buffer, count)) {
+		up(&dev->sem);
+		pr_info("fft256stream_dev_write copy_from_user exit\n");
+		return -EFAULT;
+	}
+
+	up(&dev->sem);
+	return count;
+}
+
+static ssize_t fft256stream_dev_read(struct file *fp, char __user *user_buffer,
+				     size_t count, loff_t *offset)
+{
+	struct fft_dev *dev = fp->private_data;
+	uint32_t dma_status;
+	uint32_t dma_desc_fill_level;
+	int this_count = 256;
+	int write_block_count = 0;
+	int read_block_count = 0;
+	int read_count = 0;
+	int next_fft256_buffer_offset;
+
+	if (down_interruptible(&dev->sem))
+		return -ERESTARTSYS;
+
+	/* validate count request */
+	if (count & ((this_count * 8) - 1)) {
+		up(&dev->sem);
+		return -EINVAL;
+	}
+
+	if (count > 0)
+		read_block_count = count / (this_count * 8);
+	else
+		read_block_count = 0;
+
+	write_block_count = read_block_count;
+
+	/* set the FFT length */
+	iowrite32(this_count, dev->ioremap_fft_st_adapter);
+
+	while ((write_block_count > 0) || (read_block_count > 0)) {
+		while (write_block_count > 0) {
+			if (dev->fft256_buffer_inflight_count >= 32)
+				break;
+
+			next_fft256_buffer_offset =
+			    dev->fft256_buffer_write_index * this_count * 8;
+
+			/* start the read from FFT DMA */
+			iowrite32(0x0,
+				  dev->ioremap_sgdma_from_fft_descriptor +
+				  DESC_READ_ADDRESS_REG);
+			iowrite32(dev->dma_handle + next_fft256_buffer_offset,
+				  dev->ioremap_sgdma_from_fft_descriptor +
+				  DESC_WRITE_ADDRESS_REG);
+			iowrite32(this_count * 8,
+				  dev->ioremap_sgdma_from_fft_descriptor +
+				  DESC_LENGTH_REG);
+			iowrite32(START_DMA_FROM_FFT_MASK,
+				  dev->ioremap_sgdma_from_fft_descriptor +
+				  DESC_CONTROL_REG);
+
+			/* start the write to FFT DMA */
+			iowrite32(DMA_RAM_DATA_ADDR,
+				  dev->ioremap_sgdma_to_fft_descriptor +
+				  DESC_READ_ADDRESS_REG);
+			iowrite32(0x0,
+				  dev->ioremap_sgdma_to_fft_descriptor +
+				  DESC_WRITE_ADDRESS_REG);
+			iowrite32(this_count * 4,
+				  dev->ioremap_sgdma_to_fft_descriptor +
+				  DESC_LENGTH_REG);
+			iowrite32(START_DMA_TO_FFT_MASK,
+				  dev->ioremap_sgdma_to_fft_descriptor +
+				  DESC_CONTROL_REG);
+
+			/* maintain counters and pointers */
+			write_block_count--;
+			dev->fft256_buffer_inflight_count++;
+			dev->fft256_buffer_write_index++;
+			if (dev->fft256_buffer_write_index >= 32)
+				dev->fft256_buffer_write_index = 0;
+		}
+
+		while (read_block_count > 0) {
+			if (dev->fft256_buffer_inflight_count == 0)
+				break;
+
+			if (dev->fft256_buffer_inflight_count >= 2) {
+				/* wait for at least two descriptors to be used
+				 */
+				do {
+					dma_desc_fill_level =
+					    ioread32(dev->
+						     ioremap_sgdma_from_fft_csr
+						     +
+						 CSR_DESCRIPTOR_FILL_LEVEL_REG);
+					dma_desc_fill_level &=
+					CSR_WRITE_FILL_LEVEL_MASK;
+					dma_desc_fill_level >>=
+				      CSR_WRITE_FILL_LEVEL_OFFSET;
+				} while (dma_desc_fill_level >
+					 (dev->fft256_buffer_inflight_count -
+					  2));
+			} else {
+				/* wait for all descriptors to be used */
+				do {
+					dma_desc_fill_level =
+					    ioread32(dev->
+						     ioremap_sgdma_f