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-rw-r--r--recipes-kernel/linux/config/socfpga-4.1-ltsi/patches/0001-Add-DE10-Nano-devicetree.patch143
1 files changed, 143 insertions, 0 deletions
diff --git a/recipes-kernel/linux/config/socfpga-4.1-ltsi/patches/0001-Add-DE10-Nano-devicetree.patch b/recipes-kernel/linux/config/socfpga-4.1-ltsi/patches/0001-Add-DE10-Nano-devicetree.patch
new file mode 100644
index 0000000..d41fe34
--- /dev/null
+++ b/recipes-kernel/linux/config/socfpga-4.1-ltsi/patches/0001-Add-DE10-Nano-devicetree.patch
@@ -0,0 +1,143 @@
+From ccc00a9eb345e3f45836d764211da4dd723aef52 Mon Sep 17 00:00:00 2001
+From: Dalon Westergreen <dalon.westergreen@intel.com>
+Date: Sun, 5 Feb 2017 12:30:18 -0800
+Subject: [PATCH] Add DE10-Nano devicetree
+
+Devicetree for Terasic's DE10-Nano SoC board
+
+Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
+---
+ arch/arm/boot/dts/socfpga_cyclone5_de10_nano.dts | 121 +++++++++++++++++++++++
+ 1 file changed, 121 insertions(+)
+ create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_de10_nano.dts
+
+diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/boot/dts/socfpga_cyclone5_de10_nano.dts
+new file mode 100644
+index 0000000..fe14a85
+--- /dev/null
++++ b/arch/arm/boot/dts/socfpga_cyclone5_de10_nano.dts
+@@ -0,0 +1,121 @@
++/*
++ * Copyright Intel Corporation (C) 2017. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "socfpga_cyclone5.dtsi"
++
++/ {
++ model = "Terasic DE10-Nano";
++ compatible = "altr,socfpga-cyclone5", "altr,socfpga";
++
++ chosen {
++ bootargs = "earlyprintk";
++ stdout-path = "serial0:115200n8";
++ };
++
++ memory {
++ name = "memory";
++ device_type = "memory";
++ reg = <0x0 0x40000000>; /* 1GB */
++ };
++
++ aliases {
++ ethernet0 = &gmac1;
++ };
++
++ regulator_3_3v: 3-3-v-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "3.3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ hps0 {
++ label = "hps_led0";
++ gpios = <&portb 24 0>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ keys {
++ compatible = "gpio-keys";
++ hps0 {
++ label = "hps_key0";
++ gpios = <&portb 25 0>;
++ linux,code = <63>;
++ debounce-interval = <50>;
++ };
++ };
++};
++
++&gmac1 {
++ status = "okay";
++ phy-mode = "rgmii";
++
++ txd0-skew-ps = <0>; /* -420ps */
++ txd1-skew-ps = <0>; /* -420ps */
++ txd2-skew-ps = <0>; /* -420ps */
++ txd3-skew-ps = <0>; /* -420ps */
++ rxd0-skew-ps = <420>; /* 0ps */
++ rxd1-skew-ps = <420>; /* 0ps */
++ rxd2-skew-ps = <420>; /* 0ps */
++ rxd3-skew-ps = <420>; /* 0ps */
++ txen-skew-ps = <0>; /* -420ps */
++ txc-skew-ps = <1860>; /* 960ps */
++ rxdv-skew-ps = <420>; /* 0ps */
++ rxc-skew-ps = <1680>; /* 780ps */
++
++ max-frame-size = <3800>;
++};
++
++&gpio0 {
++ status = "okay";
++};
++
++&gpio1 {
++ status = "okay";
++};
++
++&gpio2 {
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++ speed-mode = <0>;
++
++ adxl345: adxl345@0 {
++ compatible = "adi,adxl34x";
++ reg = <0x53>;
++
++ interrupt-parent = <&portc>;
++ interrupts = <3 2>;
++ };
++};
++
++&mmc0 {
++ vmmc-supply = <&regulator_3_3v>;
++ vqmmc-supply = <&regulator_3_3v>;
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&usb1 {
++ status = "okay";
++};
+--
+2.7.4
+