diff options
Diffstat (limited to 'recipes-bsp')
9 files changed, 4629 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot/files/STARTUP.BMP b/recipes-bsp/u-boot/files/STARTUP.BMP Binary files differnew file mode 100644 index 0000000..80a9e5f --- /dev/null +++ b/recipes-bsp/u-boot/files/STARTUP.BMP diff --git a/recipes-bsp/u-boot/files/STARTUP.BMP.LICENSE b/recipes-bsp/u-boot/files/STARTUP.BMP.LICENSE new file mode 100644 index 0000000..29fcda7 --- /dev/null +++ b/recipes-bsp/u-boot/files/STARTUP.BMP.LICENSE @@ -0,0 +1 @@ +Copyright 2003-2017 Terasic, Inc. All Rights Reserved. diff --git a/recipes-bsp/u-boot/files/v2017.03/0001-arm-socfpga-Move-CONFIG_EXTRA_ENV_SETTINGS-to-common.patch b/recipes-bsp/u-boot/files/v2017.03/0001-arm-socfpga-Move-CONFIG_EXTRA_ENV_SETTINGS-to-common.patch new file mode 100644 index 0000000..fd6b83f --- /dev/null +++ b/recipes-bsp/u-boot/files/v2017.03/0001-arm-socfpga-Move-CONFIG_EXTRA_ENV_SETTINGS-to-common.patch @@ -0,0 +1,102 @@ +From 59d8f9e085deb935565ebcdaaf97ff2dddaae3b8 Mon Sep 17 00:00:00 2001 +From: Dalon Westergreen <dwesterg@gmail.com> +Date: Mon, 6 Feb 2017 10:07:14 -0800 +Subject: [PATCH 1/6] arm: socfpga: Move CONFIG_EXTRA_ENV_SETTINGS to common + +Move CONFIG_EXTRA_ENV_SETTINGS to common header and add support +for distro boot. + +Add support for distro_boot in the socfpga common header. + +Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> +--- + include/configs/socfpga_common.h | 49 ++++++++++++++++++++++++++++++++++++---- + 1 file changed, 45 insertions(+), 4 deletions(-) + +diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h +index 8472b52..e0b08ec 100644 +--- a/include/configs/socfpga_common.h ++++ b/include/configs/socfpga_common.h +@@ -65,6 +65,9 @@ + #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD + #endif + ++#define CONFIG_CMD_PXE ++#define CONFIG_MENU ++ + /* + * Cache + */ +@@ -242,13 +245,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void); + * U-Boot environment + */ + #if !defined(CONFIG_ENV_SIZE) +-#define CONFIG_ENV_SIZE 4096 ++#define CONFIG_ENV_SIZE (8*1024) + #endif + + /* Environment for SDMMC boot */ + #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) +-#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +-#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ ++#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ ++#define CONFIG_ENV_OFFSET (34*512)/* just after the GPT */ + #endif + + /* Environment for QSPI boot */ +@@ -305,8 +308,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); + /* SPL SDMMC boot support */ + #ifdef CONFIG_SPL_MMC_SUPPORT + #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) +-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 + #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" ++#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 ++#endif ++#else ++#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION ++#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 + #endif + #endif + +@@ -328,4 +335,38 @@ unsigned int cm_get_qspi_controller_clk_hz(void); + */ + #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + ++/* Extra Environment */ ++#ifndef CONFIG_SPL_BUILD ++#include <config_distro_defaults.h> ++ ++#ifdef CONFIG_CMD_PXE ++#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) ++#else ++#define BOOT_TARGET_DEVICES_PXE(func) ++#endif ++ ++#define BOOT_TARGET_DEVICES(func) \ ++ func(MMC, mmc, 0) \ ++ BOOT_TARGET_DEVICES_PXE(func) \ ++ func(DHCP, dhcp, na) ++ ++#include <config_distro_bootcmd.h> ++ ++#ifndef CONFIG_EXTRA_ENV_SETTINGS ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "verify=n\0" \ ++ "bootimage=" CONFIG_BOOTFILE "\0" \ ++ "fdt_addr=100\0" \ ++ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ ++ "bootm_size=0xa000000\0" \ ++ "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ ++ "fdt_addr_r=0x02000000\0" \ ++ "scriptaddr=0x02100000\0" \ ++ "pxefile_addr_r=0x02200000\0" \ ++ "ramdisk_addr_r=0x02300000\0" \ ++ BOOTENV ++ ++#endif ++#endif ++ + #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ +-- +2.7.4 + diff --git a/recipes-bsp/u-boot/files/v2017.03/0002-arm-socfpga-Update-DE0-Nano-SoC-to-support-distro-bo.patch b/recipes-bsp/u-boot/files/v2017.03/0002-arm-socfpga-Update-DE0-Nano-SoC-to-support-distro-bo.patch new file mode 100644 index 0000000..6673905 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2017.03/0002-arm-socfpga-Update-DE0-Nano-SoC-to-support-distro-bo.patch @@ -0,0 +1,138 @@ +From 52dba58861c7c27659c30ee609c6c3438c7f88bb Mon Sep 17 00:00:00 2001 +From: Dalon Westergreen <dwesterg@gmail.com> +Date: Mon, 6 Feb 2017 22:58:15 -0800 +Subject: [PATCH 2/6] arm: socfpga: Update DE0 Nano SoC to support distro boot + +Remove CONFIG_EXTRA_ENV_SETTINGS and relly on common enironment +defined in socfpga_common.h This now suports distro boot + +Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> +--- + configs/socfpga_de0_nano_soc_defconfig | 4 ++ + include/configs/socfpga_de0_nano_soc.h | 80 +++++++++++++++++++++++++++------- + 2 files changed, 68 insertions(+), 16 deletions(-) + +diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig +index af41e1e..58139fa 100644 +--- a/configs/socfpga_de0_nano_soc_defconfig ++++ b/configs/socfpga_de0_nano_soc_defconfig +@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y + CONFIG_SPL_STACK_R_ADDR=0x00800000 + CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" ++CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de0_nano_soc.dtb" + CONFIG_FIT=y + CONFIG_SYS_CONSOLE_IS_IN_ENV=y + CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +@@ -58,3 +59,6 @@ CONFIG_G_DNL_MANUFACTURER="terasic" + CONFIG_G_DNL_VENDOR_NUM=0x0525 + CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 + CONFIG_USE_TINY_PRINTF=y ++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y ++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2 ++CONFIG_GENERIC_MMC=y +\ No newline at end of file +diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h +index f655972..b5bebbb 100644 +--- a/include/configs/socfpga_de0_nano_soc.h ++++ b/include/configs/socfpga_de0_nano_soc.h +@@ -16,9 +16,8 @@ + #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ + + /* Booting Linux */ +-#define CONFIG_BOOTFILE "fitImage" ++#define CONFIG_BOOTFILE "zImage" + #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" + #define CONFIG_LOADADDR 0x01000000 + #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +@@ -30,22 +29,71 @@ + + #define CONFIG_ENV_IS_IN_MMC + +-/* Extra Environment */ ++#ifndef CONFIG_SPL_BUILD + #define CONFIG_EXTRA_ENV_SETTINGS \ +- "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ +- "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ +- "bootm ${loadaddr} - ${fdt_addr}\0" \ +- "bootimage=zImage\0" \ ++ "verify=n\0" \ ++ "bootimage=" CONFIG_BOOTFILE "\0" \ + "fdt_addr=100\0" \ +- "fdtimage=socfpga.dtb\0" \ +- "bootm ${loadaddr} - ${fdt_addr}\0" \ +- "mmcroot=/dev/mmcblk0p2\0" \ +- "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ +- " root=${mmcroot} rw rootwait;" \ +- "bootz ${loadaddr} - ${fdt_addr}\0" \ +- "mmcload=mmc rescan;" \ +- "load mmc 0:1 ${loadaddr} ${bootimage};" \ +- "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ ++ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ ++ "bootm_size=0xa000000\0" \ ++ "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ ++ "fdt_addr_r=0x02000000\0" \ ++ "scriptaddr=0x02100000\0" \ ++ "pxefile_addr_r=0x02200000\0" \ ++ "ramdisk_addr_r=0x02300000\0" \ ++ \ ++ "fpga_cfg=" \ ++ "env exists fpga_files || setenv fpga_files " \ ++ "${board}.rbf; " \ ++ "for target in ${boot_targets}; do " \ ++ "run fpga_cfg_${target}; " \ ++ "done\0" \ ++ \ ++ "fpga_cfg_mmc0=" \ ++ "setenv devnum 0; " \ ++ "setenv devtype mmc; " \ ++ "run scan_dev_for_boot_part_fpga\0" \ ++ \ ++ "scan_dev_for_boot_part_fpga=" \ ++ "part list ${devtype} ${devnum} -bootable devplist; " \ ++ "env exists devplist || setenv devplist 1; " \ ++ "for distro_bootpart in ${devplist}; do " \ ++ "if fstype ${devtype} " \ ++ "${devnum}:${distro_bootpart} " \ ++ "bootfstype; then " \ ++ "run scan_dev_for_boot_fpga; " \ ++ "fi; " \ ++ "done\0" \ ++ \ ++ "scan_dev_for_boot_fpga=" \ ++ "echo Scanning ${devtype} " \ ++ "${devnum}:${distro_bootpart}...; " \ ++ "for prefix in ${boot_prefixes}; do " \ ++ "run scan_dev_for_fpga; " \ ++ "done\0" \ ++ \ ++ "scan_dev_for_fpga=" \ ++ "for file in ${fpga_files}; do " \ ++ "if test -e ${devtype} " \ ++ "${devnum}:${distro_bootpart} " \ ++ "${prefix}${file}; then " \ ++ "echo Found FPGA Configuration " \ ++ "${prefix}${file}; " \ ++ "load ${devtype} " \ ++ "${devnum}:${distro_bootpart} " \ ++ "${kernel_addr_r} " \ ++ "${prefix}${file}; " \ ++ "fpga load 0 ${kernel_addr_r} " \ ++ "${filesize}; " \ ++ "bridge enable; " \ ++ "fi; " \ ++ "done\0" \ ++ \ ++ BOOTENV ++ ++#endif ++ ++#define CONFIG_BOOTCOMMAND "run fpga_cfg; run distro_bootcmd" + + /* The rest of the configuration is shared */ + #include <configs/socfpga_common.h> +-- +2.7.4 + diff --git a/recipes-bsp/u-boot/files/v2017.03/0003-arm-socfpga-add-support-for-Terasic-DE10-Nano-board.patch b/recipes-bsp/u-boot/files/v2017.03/0003-arm-socfpga-add-support-for-Terasic-DE10-Nano-board.patch new file mode 100644 index 0000000..62110bc --- /dev/null +++ b/recipes-bsp/u-boot/files/v2017.03/0003-arm-socfpga-add-support-for-Terasic-DE10-Nano-board.patch @@ -0,0 +1,1720 @@ +From 20529989acfe244ecd6e21baabc702dabca9ff02 Mon Sep 17 00:00:00 2001 +From: Dalon Westergreen <dwesterg@gmail.com> +Date: Wed, 4 Jan 2017 20:47:51 -0800 +Subject: [PATCH 3/6] arm: socfpga: add support for Terasic DE10-Nano board + +Add CycloneV based Terasic DE10 Nano board. The +board is based on the DE0 Nano but has a larger +fpga. + +Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> +--- + .gitignore | 3 + + arch/arm/dts/Makefile | 1 + + arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 68 +++ + arch/arm/mach-socfpga/Kconfig | 7 + + board/terasic/de10-nano/MAINTAINERS | 5 + + board/terasic/de10-nano/Makefile | 9 + + board/terasic/de10-nano/qts/iocsr_config.h | 660 ++++++++++++++++++++++++++++ + board/terasic/de10-nano/qts/pinmux_config.h | 219 +++++++++ + board/terasic/de10-nano/qts/pll_config.h | 85 ++++ + board/terasic/de10-nano/qts/sdram_config.h | 344 +++++++++++++++ + board/terasic/de10-nano/socfpga.c | 6 + + configs/socfpga_de10_nano_defconfig | 62 +++ + include/configs/socfpga_de10_nano.h | 101 +++++ + 13 files changed, 1570 insertions(+) + create mode 100644 arch/arm/dts/socfpga_cyclone5_de10_nano.dts + create mode 100644 board/terasic/de10-nano/MAINTAINERS + create mode 100644 board/terasic/de10-nano/Makefile + create mode 100644 board/terasic/de10-nano/qts/iocsr_config.h + create mode 100644 board/terasic/de10-nano/qts/pinmux_config.h + create mode 100644 board/terasic/de10-nano/qts/pll_config.h + create mode 100644 board/terasic/de10-nano/qts/sdram_config.h + create mode 100644 board/terasic/de10-nano/socfpga.c + create mode 100644 configs/socfpga_de10_nano_defconfig + create mode 100644 include/configs/socfpga_de10_nano.h + +diff --git a/.gitignore b/.gitignore +index 7fac5b3..6cc6cd7 100644 +--- a/.gitignore ++++ b/.gitignore +@@ -84,3 +84,6 @@ GTAGS + *.orig + *~ + \#*# ++ ++# DS5 script ++uboot.ds +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 0fbbb9b..d700ecc 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -149,6 +149,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ + socfpga_cyclone5_socdk.dtb \ + socfpga_cyclone5_de0_nano_soc.dtb \ + socfpga_cyclone5_de1_soc.dtb \ ++ socfpga_cyclone5_de10_nano.dtb \ + socfpga_cyclone5_sockit.dtb \ + socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_sr1500.dtb \ +diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +new file mode 100644 +index 0000000..ee62a50 +--- /dev/null ++++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +@@ -0,0 +1,68 @@ ++/* ++ * Copyright (C) 2017, Intel Corporation ++ * ++ * based on socfpga_cyclone5_de0_nano_soc.dts ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include "socfpga_cyclone5.dtsi" ++ ++/ { ++ model = "Terasic DE10-Nano"; ++ compatible = "altr,socfpga-cyclone5", "altr,socfpga"; ++ ++ chosen { ++ bootargs = "console=ttyS0,115200"; ++ }; ++ ++ aliases { ++ ethernet0 = &gmac1; ++ udc0 = &usb1; ++ }; ++ ++ memory { ++ name = "memory"; ++ device_type = "memory"; ++ reg = <0x0 0x40000000>; /* 1GB */ ++ }; ++ ++ soc { ++ u-boot,dm-pre-reloc; ++ }; ++}; ++ ++&gmac1 { ++ status = "okay"; ++ phy-mode = "rgmii"; ++ ++ rxd0-skew-ps = <420>; ++ rxd1-skew-ps = <420>; ++ rxd2-skew-ps = <420>; ++ rxd3-skew-ps = <420>; ++ txen-skew-ps = <0>; ++ txc-skew-ps = <1860>; ++ rxdv-skew-ps = <420>; ++ rxc-skew-ps = <1680>; ++}; ++ ++&gpio0 { ++ status = "okay"; ++}; ++ ++&gpio1 { ++ status = "okay"; ++}; ++ ++&gpio2 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ status = "okay"; ++ u-boot,dm-pre-reloc; ++}; ++ ++&usb1 { ++ status = "okay"; ++}; +diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig +index e56b3db..6a776b5 100644 +--- a/arch/arm/mach-socfpga/Kconfig ++++ b/arch/arm/mach-socfpga/Kconfig +@@ -85,6 +85,10 @@ config TARGET_SOCFPGA_TERASIC_DE1_SOC + bool "Terasic DE1-SoC (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + ++config TARGET_SOCFPGA_TERASIC_DE10_NANO ++ bool "Terasic DE10-Nano (Cyclone V)" ++ select TARGET_SOCFPGA_CYCLONE5 ++ + config TARGET_SOCFPGA_TERASIC_SOCKIT + bool "Terasic SoCkit (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 +@@ -96,6 +100,7 @@ config SYS_BOARD + default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO + default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC ++ default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO + default "is1" if TARGET_SOCFPGA_IS1 + default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK + default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT +@@ -112,6 +117,7 @@ config SYS_VENDOR + default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO + default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC + default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT ++ default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO + + config SYS_SOC + default "socfpga" +@@ -121,6 +127,7 @@ config SYS_CONFIG_NAME + default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO + default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC ++ default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO + default "socfpga_is1" if TARGET_SOCFPGA_IS1 + default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK + default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT +diff --git a/board/terasic/de10-nano/MAINTAINERS b/board/terasic/de10-nano/MAINTAINERS +new file mode 100644 +index 0000000..f4dd0df +--- /dev/null ++++ b/board/terasic/de10-nano/MAINTAINERS +@@ -0,0 +1,5 @@ ++DE10-NANO BOARD ++M: Dalon Westergreen <dwesterg@gmail.com> ++S: Maintained ++F: include/configs/socfpga_de10_nano.h ++F: configs/socfpga_de10_nano_defconfig +diff --git a/board/terasic/de10-nano/Makefile b/board/terasic/de10-nano/Makefile +new file mode 100644 +index 0000000..86f9b78 +--- /dev/null ++++ b/board/terasic/de10-nano/Makefile +@@ -0,0 +1,9 @@ ++# ++# (C) Copyright 2001-2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y := socfpga.o +diff --git a/board/terasic/de10-nano/qts/iocsr_config.h b/board/terasic/de10-nano/qts/iocsr_config.h +new file mode 100644 +index 0000000..7e049bf +--- /dev/null ++++ b/board/terasic/de10-nano/qts/iocsr_config.h +@@ -0,0 +1,660 @@ ++/* ++ * Altera SoCFPGA IOCSR configuration ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef __SOCFPGA_IOCSR_CONFIG_H__ ++#define __SOCFPGA_IOCSR_CONFIG_H__ ++ ++#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 ++#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 ++#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 ++#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 ++ ++const unsigned long iocsr_scan_chain0_table[] = { ++ 0x00000000, ++ 0x00000000, ++ 0x0FF00000, ++ 0xC0000000, ++ 0x0000003F, ++ 0x00008000, ++ 0x00020080, ++ 0x18060000, ++ 0x08000000, ++ 0x00018020, ++ 0x00000000, ++ 0x00004000, ++ 0x00010040, ++ 0x04010000, ++ 0x04000000, ++ 0x00000010, ++ 0x00004010, ++ 0x00002000, ++ 0x00020000, ++ 0x02008000, ++ 0x02000000, ++ 0x00000008, ++ 0x00002008, ++ 0x00001000, ++}; ++ ++const unsigned long iocsr_scan_chain1_table[] = { ++ 0x00100000, ++ 0x10040000, ++ 0x100000C0, ++ 0x00000040, ++ 0x00010040, ++ 0x00008000, ++ 0x00060180, ++ 0x20000000, ++ 0x00000000, ++ 0x00000080, ++ 0x00020000, ++ 0x00004000, ++ 0x00010040, ++ 0x10000000, ++ 0x04000000, ++ 0x00000010, ++ 0x00004010, ++ 0x00002000, ++ 0x00020000, ++ 0x06018000, ++ 0x01FE0000, ++ 0xF8000000, ++ 0x00000007, ++ 0x00001000, ++ 0x00010000, ++ 0x04000000, ++ 0x00000000, ++ 0x00000010, ++ 0x00004000, ++ 0x00000800, ++ 0x00000000, ++ 0x00000000, ++ 0x00000000, ++ 0x00000008, ++ 0x00002000, ++ 0x00000400, ++ 0x00000000, ++ 0x00401000, ++ 0x00000003, ++ 0x00000000, ++ 0x00000000, ++ 0x00000200, ++ 0x00600802, ++ 0x00000000, ++ 0x80200000, ++ 0x80000600, ++ 0x00000200, ++ 0x00000100, ++ 0x00300401, ++ 0xC0100400, ++ 0x40100000, ++ 0x40000300, ++ 0x000C0100, ++ 0x00000080, ++}; ++ ++const unsigned long iocsr_scan_chain2_table[] = { ++ 0x300C0300, ++ 0x00000000, ++ 0x0FF00000, ++ 0x00000000, ++ 0x0C0300C0, ++ 0x00008000, ++ 0x00080000, ++ 0x18060000, ++ 0x18000000, ++ 0x00018060, ++ 0x00020000, ++ 0x00004000, ++ 0x200300C0, ++ 0x10000000, ++ 0x00000000, ++ 0x00000040, ++ 0x00010000, ++ 0x00002000, ++ 0x10018060, ++ 0x06018000, ++ 0x06000000, ++ 0x00010018, ++ 0x00006018, ++ 0x00001000, ++ 0x00010000, ++ 0x00000000, ++ 0x03000000, ++ 0x0000800C, ++ 0x00C01004, ++ 0x00000800, ++}; ++ ++const unsigned long iocsr_scan_chain3_table[] = { ++ 0x0C420D80, ++ 0x082000FF, ++ 0x0A804001, ++ 0x07900000, ++ 0x08020000, ++ 0x00100000, ++ 0x0A800000, ++ 0x07900000, ++ 0x08020000, ++ 0x00100000, ++ 0xC8800000, ++ 0x00003001, ++ 0x00C00722, ++ 0x00000000, ++ 0x00000021, ++ 0x82000004, ++ 0x05400000, ++ 0x03C80000, ++ 0x04010000, ++ 0x00080000, ++ 0x05400000, ++ 0x03C80000, ++ 0x05400000, ++ 0x03C80000, ++ 0xE4400000, ++ 0x00001800, ++ 0x00600391, ++ 0x800E4400, ++ 0x00000001, ++ 0x40000002, ++ 0x02A00000, ++ 0x01E40000, ++ 0x02A00000, ++ 0x01E40000, ++ 0x02A00000, ++ 0x01E40000, ++ 0x02A00000, ++ 0x01E40000, ++ 0x72200000, ++ 0x80000C00, ++ 0x003001C8, ++ 0xC0072200, ++ 0x1C880000, ++ 0x20000300, ++ 0x00040000, ++ 0x50670000, ++ 0x00000010, ++ 0x24590000, ++ 0x00001000, ++ 0xA0000034, ++ 0x0D000001, ++ 0xC0680618, ++ 0x45034071, ++ 0x0A281A01, ++ 0x806180D0, ++ 0x34071C06, ++ 0x01A034D0, ++ 0x180D0000, ++ 0x71C06806, ++ 0x01450340, ++ 0xD000001A, ++ 0x0680E380, ++ 0x10040000, ++ 0x00200000, ++ 0x10040000, ++ 0x00200000, ++ 0x15000000, ++ 0x0F200000, ++ 0x15000000, ++ 0x0F200000, ++ 0x01FE0000, ++ 0x00000000, ++ 0x01800E44, ++ 0x00391000, ++ 0x007F8006, ++ 0x00000000, ++ 0x0A800001, ++ 0x07900000, ++ 0x0A800000, ++ 0x07900000, ++ 0x0A800000, ++ 0x07900000, ++ 0x08020000, ++ 0x00100000, ++ 0xC8800000, ++ 0x00003001, ++ 0x00C00722, ++ 0x00000FF0, ++ 0x72200000, ++ 0x80000C00, ++ 0x05400000, ++ 0x02480000, ++ 0x04000000, ++ 0x00080000, ++ 0x05400000, ++ 0x03C80000, ++ 0x05400000, ++ 0x03C80000, ++ 0x6A1C0000, ++ 0x00001800, ++ 0x00600391, ++ 0x800E4400, ++ 0x1A870001, ++ 0x40000600, ++ 0x02A00040, ++ 0x01E40000, ++ 0x02A00000, ++ 0x01E40000, ++ 0x02A00000, ++ 0x01E40000, ++ 0x02A00000, ++ 0x01E40000, ++ 0x72200000, ++ 0x80000C00, ++ 0x003001C8, ++ 0xC0072200, ++ 0x1C880000, ++ 0x20000300, ++ 0x00040000, ++ 0x50670000, ++ 0x00000010, ++ 0x24590000, ++ 0x00001000, ++ 0xA0000034, ++ 0x0D000001, ++ 0xC0680618, ++ 0x45034071, ++ 0x0A281A01, ++ 0x806180D0, ++ 0x34071C06, ++ 0x01A00040, ++ 0x180D0002, ++ 0x71C06806, ++ 0x01450340, ++ 0xD00A281A, ++ 0x06806180, ++ 0x10040000, ++ 0x00200000, ++ 0x10040000, ++ 0x00200000, ++ 0x15000000, ++ 0x0F200000, ++ 0x15000000, ++ 0x0F200000, ++ 0x01FE0000, ++ 0x00000000, ++ 0x01800E44, ++ 0x00391000, ++ 0x007F8006, ++ 0x00000000, ++ 0x99300001, ++ 0x34343400, ++ 0xAA0D4000, ++ 0x01C3A800, ++ 0xAA0D4000, ++ 0x01C3A800, ++ 0xAA0D4000, ++ 0x01C3A800, ++ 0x00040100, ++ 0x00000800, ++ 0x00000000, ++ 0x00001208, ++ 0x00482000, ++ 0x01000000, ++ 0x00000000, ++ 0x00410482, ++ 0x0006A000, ++ 0x0001B400, ++ 0x00020000, ++ 0x00000400, ++ 0x0002A000, ++ 0x0001E400, ++ 0x5506A000, ++ 0x00E1D400, ++ 0x00000000, ++ 0xC880090C, ++ 0x00003001, ++ 0x90400000, ++ 0x00000000, ++ 0x2020C243, ++ 0x2A835000, ++ 0x0070EA00, ++ 0x2A835000, ++ 0x0070EA00, ++ 0x2A835000, ++ 0x0070EA00, ++ 0x00010040, ++ 0x00000200, ++ 0x00000000, ++ 0x00000482, ++ 0x00120800, ++ 0x00002000, ++ 0x80000000, ++ 0x00104120, ++ 0x00000200, ++ 0xAC0D5F80, ++ 0xFFFFFFFF, ++ 0x14F3690D, ++ 0x1A041414, ++ 0x00D00000, ++ 0x0C864000, ++ 0x79E47A03, ++ 0xCAAAA3DD, ++ 0xF6D5551E, ++ 0x0352D348, ++ 0x821A0000, ++ 0x0000D000, ++ 0x030C0680, ++ 0xD559647A, ++ 0x1ECAAAA3, ++ 0xC8F6D965, ++ 0x00034AB2, ++ 0x00080200, ++ 0x00001000, ++ 0x00080200, ++ 0x00001000, ++ 0x000A8000, ++ 0x00075000, ++ 0x541A8000, ++ 0x03875001, ++ 0x10000000, ++ 0x00000000, ++ 0x0080C000, ++ 0x41000000, ++ 0x00003FC2, ++ 0x00820000, ++ 0xAA0D4000, ++ 0x01C3A800, ++ 0xAA0D4000, ++ 0x01C3A800, ++ 0xAA0D4000, ++ 0x01C3A800, ++ 0x00040100, ++ 0x00000800, ++ 0x00000000, ++ 0x00001208, ++ 0x00482000, ++ 0x00008000, ++ 0x00000000, ++ 0x00410482, ++ 0x0006A000, ++ 0x0001B400, ++ 0x00020000, ++ 0x00000400, ++ 0x00020080, ++ 0x00000400, ++ 0x5506A000, ++ 0x00E1D400, ++ 0x00000000, ++ 0x0000090C, ++ 0x00000010, ++ 0x90400000, ++ 0x00000000, ++ 0x2020C243, ++ 0x2A835000, ++ 0x0070EA00, ++ 0x2A835000, ++ 0x0070EA00, ++ 0x2A835000, ++ 0x0070EA00, ++ 0x00015000, ++ 0x0000F200, ++ 0x00000000, ++ 0x00000482, ++ 0x00120800, ++ 0x00600391, ++ 0x80000000, ++ 0x00104120, ++ 0x00000200, ++ 0xAC0D5F80, ++ 0xFFFFFFFF, ++ 0x14F3690D, ++ 0x1A041414, ++ 0x00D00000, ++ 0x0C864000, ++ 0x79E47A03, ++ 0x8B2CA3DD, ++ 0xF6D9651E, ++ 0x034AB2C8, ++ 0x821A0041, ++ 0x0000D000, ++ 0x00000680, ++ 0xD559647A, ++ 0x1E8B2CA3, ++ 0xC8F6D965, ++ 0x00034AB2, ++ 0x00080200, ++ 0x00001000, ++ 0x00080200, ++ 0x00001000, ++ 0x000A8000, ++ 0x00075000, ++ 0x541A8000, ++ 0x03875001, ++ 0x10000000, ++ 0x00000000, ++ 0x0080C000, ++ 0x41000000, ++ 0x04000002, ++ 0x00820000, ++ 0xAA0D4000, ++ 0x01C3A800, ++ 0xAA0D4000, ++ 0x01C3A800, ++ 0xAA0D4000, ++ 0x01C3A800, ++ 0x00040100, ++ 0x00000800, ++ 0x00000000, ++ 0x00001208, ++ 0x00482000, ++ 0x00008000, ++ 0x00000000, ++ 0x00410482, ++ 0x0006A000, ++ 0x0001B400, ++ 0x00020000, ++ 0x00000400, ++ 0x0002A000, ++ 0x0001E400, ++ 0x5506A000, ++ 0x00E1D400, ++ 0x00000000, ++ 0xC880090C, ++ 0x00003001, ++ 0x90400000, ++ 0x00000000, ++ 0x2020C243, ++ 0x2A835000, ++ 0x0070EA00, ++ 0x2A835000, ++ 0x0070EA00, ++ 0x2A835000, ++ 0x0070EA00, ++ 0x00010040, ++ 0x00000200, ++ 0x00000000, ++ 0x00000482, ++ 0x00120800, ++ 0x00002000, ++ 0x80000000, ++ 0x00104120, ++ 0x00000200, ++ 0xAC0D5F80, ++ 0xFFFFFFFF, ++ 0x14F3690D, ++ 0x1A041414, ++ 0x00D00000, ++ 0x14864000, ++ 0x59647A05, ++ 0x8AAAA3D5, ++ 0xF6D9651E, ++ 0x034AB2C8, ++ 0x821A0000, ++ 0x0000D000, ++ 0x00000680, ++ 0xD559647A, ++ 0x1E8B2CA3, ++ 0xC8F6D965, ++ 0x00034AB2, ++ 0x00080200, ++ 0x00001000, ++ 0x00080200, ++ 0x00001000, ++ 0x000A8000, ++ 0x00075000, ++ 0x541A8000, ++ 0x03875001, ++ 0x10000000, ++ 0x00000000, ++ 0x0080C000, ++ 0x41000000, ++ 0x04000002, ++ 0x00820000, ++ 0xAA0D4000, ++ 0x01C3A800, ++ 0xAA0D4000, ++ 0x01C3A800, ++ 0xAA0D4000, ++ 0x01C3A800, ++ 0x00040100, ++ 0x00000800, ++ 0x00000000, ++ 0x00001208, ++ 0x00482000, ++ 0x00008000, ++ 0x00000000, ++ 0x00410482, ++ 0x0006A000, ++ 0x0001B400, ++ 0x00020000, ++ 0x00000400, ++ 0x00020080, ++ 0x00000400, ++ 0x5506A000, ++ 0x00E1D400, ++ 0x00000000, ++ 0x0000090C, ++ 0x00000010, ++ 0x90400000, ++ 0x00000000, ++ 0x2020C243, ++ 0x2A835000, ++ 0x0070EA00, ++ 0x2A835000, ++ 0x0070EA00, ++ 0x2A835000, ++ 0x0070EA00, ++ 0x00010040, ++ 0x00000200, ++ 0x00000000, ++ 0x00000482, ++ 0x00120800, ++ 0x00400000, ++ 0x80000000, ++ 0x00104120, ++ 0x00000200, ++ 0xAC0D5F80, ++ 0xFFFFFFFF, ++ 0x14F1690D, ++ 0x1A041414, ++ 0x00D00000, ++ 0x14864000, ++ 0x59647A05, ++ 0x8B2CA3D5, ++ 0xF6D9651E, ++ 0x0352D348, ++ 0x821A0000, ++ 0x0000D000, ++ 0x00000680, ++ 0xD559647A, ++ 0x1E8B2CA3, ++ 0x48F6D965, ++ 0x000352D3, ++ 0x00080200, ++ 0x00001000, ++ 0x00080200, ++ 0x00001000, ++ 0x000A8000, ++ 0x00075000, ++ 0x541A8000, ++ 0x03875001, ++ 0x10000000, ++ 0x00000000, ++ 0x0080C000, ++ 0x41000000, ++ 0x04000002, ++ 0x00820000, ++ 0x00489800, ++ 0x801A1A1A, ++ 0x00000200, ++ 0x80000004, ++ 0x00000200, ++ 0x80000004, ++ 0x00000200, ++ 0x80000004, ++ 0x00000200, ++ 0x00000004, ++ 0x00040000, ++ 0x10000000, ++ 0x00000000, ++ 0x00000040, ++ 0x00010000, ++ 0x40002000, ++ 0x00000100, ++ 0x40000002, ++ 0x00000100, ++ 0x40000002, ++ 0x00000100, ++ 0x40000002, ++ 0x00000100, ++ 0x00000002, ++ 0x00020000, ++ 0x08000000, ++ 0x00000000, ++ 0x00000020, ++ 0x00008000, ++ 0x20001000, ++ 0x00000080, ++ 0x20000001, ++ 0x00000080, ++ 0x20000001, ++ 0x00000080, ++ 0x20000001, ++ 0x00000080, ++ 0x00000001, ++ 0x00010000, ++ 0x04000000, ++ 0x00FF0000, ++ 0x00000000, ++ 0x00004000, ++ 0x00000800, ++ 0xC0000001, ++ 0x00041419, ++ 0x40000000, ++ 0x04000816, ++ 0x000D0000, ++ 0x00006800, ++ 0x00000340, ++ 0xD000001A, ++ 0x06800000, ++ 0x00340000, ++ 0x0001A000, ++ 0x00000D00, ++ 0x40000068, ++ 0x1A000003, ++ 0x00D00000, ++ 0x00068000, ++ 0x00003400, ++ 0x000001A0, ++ 0x00000401, ++ 0x00000008, ++ 0x00000401, ++ 0x00000008, ++ 0x00000401, ++ 0x00000008, ++ 0x00000401, ++ 0x80000008, ++ 0x0000007F, ++ 0x20000000, ++ 0x00000000, ++ 0xE0000080, ++ 0x0000001F, ++ 0x00004000, ++}; ++ ++ ++#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ +diff --git a/board/terasic/de10-nano/qts/pinmux_config.h b/board/terasic/de10-nano/qts/pinmux_config.h +new file mode 100644 +index 0000000..b8f5ea1 +--- /dev/null ++++ b/board/terasic/de10-nano/qts/pinmux_config.h +@@ -0,0 +1,219 @@ ++/* ++ * Altera SoCFPGA PinMux configuration ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef __SOCFPGA_PINMUX_CONFIG_H__ ++#define __SOCFPGA_PINMUX_CONFIG_H__ ++ ++const u8 sys_mgr_init_table[] = { ++ 0, /* EMACIO0 */ ++ 2, /* EMACIO1 */ ++ 2, /* EMACIO2 */ ++ 2, /* EMACIO3 */ ++ 2, /* EMACIO4 */ ++ 2, /* EMACIO5 */ ++ 2, /* EMACIO6 */ ++ 2, /* EMACIO7 */ ++ 2, /* EMACIO8 */ ++ 0, /* EMACIO9 */ ++ 2, /* EMACIO10 */ ++ 2, /* EMACIO11 */ ++ 2, /* EMACIO12 */ ++ 2, /* EMACIO13 */ ++ 0, /* EMACIO14 */ ++ 0, /* EMACIO15 */ ++ 0, /* EMACIO16 */ ++ 0, /* EMACIO17 */ ++ 0, /* EMACIO18 */ ++ 0, /* EMACIO19 */ ++ 3, /* FLASHIO0 */ ++ 0, /* FLASHIO1 */ ++ 3, /* FLASHIO2 */ ++ 3, /* FLASHIO3 */ ++ 0, /* FLASHIO4 */ ++ 0, /* FLASHIO5 */ ++ 0, /* FLASHIO6 */ ++ 0, /* FLASHIO7 */ ++ 0, /* FLASHIO8 */ ++ 3, /* FLASHIO9 */ ++ 3, /* FLASHIO10 */ ++ 3, /* FLASHIO11 */ ++ 0, /* GENERALIO0 */ ++ 1, /* GENERALIO1 */ ++ 1, /* GENERALIO2 */ ++ 1, /* GENERALIO3 */ ++ 1, /* GENERALIO4 */ ++ 0, /* GENERALIO5 */ ++ 0, /* GENERALIO6 */ ++ 1, /* GENERALIO7 */ ++ 1, /* GENERALIO8 */ ++ 0, /* GENERALIO9 */ ++ 0, /* GENERALIO10 */ ++ 0, /* GENERALIO11 */ ++ 0, /* GENERALIO12 */ ++ 0, /* GENERALIO13 */ ++ 0, /* GENERALIO14 */ ++ 1, /* GENERALIO15 */ ++ 1, /* GENERALIO16 */ ++ 1, /* GENERALIO17 */ ++ 1, /* GENERALIO18 */ ++ 0, /* GENERALIO19 */ ++ 0, /* GENERALIO20 */ ++ 0, /* GENERALIO21 */ ++ 0, /* GENERALIO22 */ ++ 0, /* GENERALIO23 */ ++ 0, /* GENERALIO24 */ ++ 0, /* GENERALIO25 */ ++ 0, /* GENERALIO26 */ ++ 0, /* GENERALIO27 */ ++ 0, /* GENERALIO28 */ ++ 0, /* GENERALIO29 */ ++ 0, /* GENERALIO30 */ ++ 0, /* GENERALIO31 */ ++ 2, /* MIXED1IO0 |
