diff options
Diffstat (limited to 'recipes-bsp/u-boot/files/v2017.03/0006-arm-socfpga-fix-issue-with-warm-reset-when-CSEL-is-0.patch')
| -rw-r--r-- | recipes-bsp/u-boot/files/v2017.03/0006-arm-socfpga-fix-issue-with-warm-reset-when-CSEL-is-0.patch | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/recipes-bsp/u-boot/files/v2017.03/0006-arm-socfpga-fix-issue-with-warm-reset-when-CSEL-is-0.patch b/recipes-bsp/u-boot/files/v2017.03/0006-arm-socfpga-fix-issue-with-warm-reset-when-CSEL-is-0.patch new file mode 100644 index 0000000..62ae258 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2017.03/0006-arm-socfpga-fix-issue-with-warm-reset-when-CSEL-is-0.patch @@ -0,0 +1,66 @@ +From 968523984023e1107651216a9b6a0e4816ffe1a6 Mon Sep 17 00:00:00 2001 +From: Dalon Westergreen <dwesterg@gmail.com> +Date: Fri, 17 Feb 2017 17:02:29 -0800 +Subject: [PATCH 6/6] arm: socfpga: fix issue with warm reset when CSEL is 0 + +When CSEL=0x0 the socfpga bootrom does not touch the clock +configuration for the device. This can lead to a boot failure +on warm resets. This patch disables warm resets when CSEL=0. +This results in the clock and pll configurations being reset +on any reset issued when CSEL=0. + +Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> +--- + arch/arm/mach-socfpga/include/mach/system_manager.h | 3 +++ + arch/arm/mach-socfpga/misc.c | 13 ++++++++++++- + 2 files changed, 15 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h +index c45edea..c9c0b33 100644 +--- a/arch/arm/mach-socfpga/include/mach/system_manager.h ++++ b/arch/arm/mach-socfpga/include/mach/system_manager.h +@@ -137,6 +137,9 @@ struct socfpga_system_manager { + + #define SYSMGR_SDMMC_DRVSEL_SHIFT 0 + ++#define SYSMGR_BOOTINFO_CSEL_MASK 0x18 ++#define SYSMGR_BOOTINFO_CSEL_LSB 3 ++ + /* EMAC Group Bit definitions */ + #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 + #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c +index dd6b53b..9792138 100644 +--- a/arch/arm/mach-socfpga/misc.c ++++ b/arch/arm/mach-socfpga/misc.c +@@ -356,6 +356,7 @@ static uint32_t iswgrp_handoff[8]; + int arch_early_init_r(void) + { + int i; ++ unsigned int csel; + + /* + * Write magic value into magic register to unlock support for +@@ -363,8 +364,18 @@ int arch_early_init_r(void) + * value to be written into the register by the bootloader, so + * to support that old code, we write it here instead of in the + * reset_cpu() function just before resetting the CPU. ++ * ++ * For CSEL = 0 we do not want to enable warm resets to ensure that ++ * on reset the clocks and plls are reset to their default states as ++ * the bootrom, for CSEL=0, leaves the clocks untouched. If the clocks ++ * and plls are not reset, the bootrom will fail to load the spl image. + */ +- writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); ++ ++ csel = (readl(&sysmgr_regs->bootinfo) & SYSMGR_BOOTINFO_CSEL_MASK) >> ++ SYSMGR_BOOTINFO_CSEL_LSB; ++ ++ if (csel) ++ writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); + + for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ + iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); +-- +2.7.4 + |