Initial commit of de10-nano recipes

Please note that this is purely for development.  Only superficial
efforts have been made to resolve security concerns, and it should
be noted that the board ships with an EMPTY ROOT PASSWORD and support
for root login via ssh.  This allows passwordless access to the board
via ssh.

recipes-bsp/u-boot:
Contains the uboot 2017.03rc2 recipe and patches to support the
de10-nano board

recipes-connectivity/avahi:
bbappend to remove unwanted packages

recipes-connectivity/bluez:
bbappend to add --compat to the bluetooth service to support legacy
SDP APIs

recipes-connectivity/openssh:
bbappend to add a custom sshd_config

recipes-core/base-files:
bbappend to customize fstab and inputrc

recipes-core/imagemagick:
bbappend to change build configuration for the de10-nano board

recipes-core/packagegroups:
bbappend to remove an unwanted package

recipes-core/webkit:
bbappend to remove support for opengl

recipes-demo:
Various demo applications

recipes-devtools:
MRAA and UPM recipes

recipes-images/angstrom/de10-nano-image.bb:
DE10-Nano image definition

recipes-kernel/de10-nano-linux-firmware:
FPGA related firmware required for fpga configuration and devicetree
overlay support

recipes-kernel/linux:
bbappend to customize configuration of linux kernel as well as patch
in the de10-nano devicetree

recipes-misc:
various initialization and systemd scripts

recipes-qt/qt5:
bbappend to modify qt build options

recipes-support/neon:
bbappend to remove unwanted package

recipes-support/upower:
bbappend to remove unwanted package

recipes-webserver:
webserver configuration and webcontent for board hostedweb portal

recipes-xfce/thunar-volman:
bbappend to remove unwanted package

recipes-xfce/xfce-pointers:
add configuration so that xfce does not use the adxl input as a mouse

recipes-xfce/xfce4-settings:
bbappend to remove unwanted package

Signed-off-by: Westergreen, Dalon <dalon.westergreen@intel.com>

1 files changed, 76 insertions, 0 deletions

diff --git a/recipes-demo/de10-nano-fftdriver-mod/files/fft_driver.h b/recipes-demo/de10-nano-fftdriver-mod/files/fft_driver.h
new file mode 100644
index 0000000..499c5d0
--- /dev/null
+++ b/recipes-demo/de10-nano-fftdriver-mod/files/fft_driver.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * PERIPHBASE and Global Timer offset
+ */
+#define PERIPHBASE		(0xFFFEC000)
+#define GLOBAL_TIMER_OFFSET	(0x200)
+
+/*
+ * msgdma driver values
+ */
+#define DMA_BUFFER_ALLOC_SIZE	(64 *1024)
+#define DMA_ACP_OFFSET		(0x40000000)
+
+#define DMA_DATA_OFFSET		(0 * 1024)
+#define DMA_RESULT_OFFSET	(32 * 1024)
+#define DMA_RESULT_SPAN		(32 * 1024)
+
+#define DMA_DATA_RAM_OFFSET	(0x40000)
+#define DMA_RAM_DATA_ADDR	(DMA_DATA_RAM_OFFSET + DMA_DATA_OFFSET)
+#define DMA_RAM_RESULTS_ADDR	(DMA_DATA_RAM_OFFSET + DMA_RESULT_OFFSET)
+
+#define CSR_STATUS_REG			(0x0 << 2)
+#define CSR_CONTROL_REG			(0x1 << 2)
+#define CSR_DESCRIPTOR_FILL_LEVEL_REG	(0x2 << 2)
+#define CSR_RESPONSE_FILL_LEVEL_REG	(0x3 << 2)
+
+#define DESC_READ_ADDRESS_REG		(0x0 << 2)
+#define DESC_WRITE_ADDRESS_REG		(0x1 << 2)
+#define DESC_LENGTH_REG			(0x2 << 2)
+#define DESC_CONTROL_REG		(0x3 << 2)
+
+#define DESC_CTRL_GENERATE_SOP_MASK	(1 << 8)
+#define DESC_CTRL_GENERATE_EOP_MASK	(1 << 9)
+#define DESC_CTRL_END_ON_EOP_MASK	(1 << 12)
+#define DESC_CTRL_GO_MASK		(1 << 31)
+
+#define CSR_BUSY_MASK                           1
+#define CSR_DESCRIPTOR_BUFFER_EMPTY_MASK        (1 << 1)
+#define CSR_GLOBAL_INTERRUPT_MASK               (1 << 4)
+#define CSR_IRQ_SET_MASK                        (1 << 9)
+#define CSR_RESET_MASK                          (1 << 1)
+#define CSR_RESET_STATE_MASK                    (1 << 6)
+#define CSR_STOP_DESCRIPTORS_MASK               (1 << 5)
+#define CSR_STOP_MASK                           1
+#define CSR_STOP_ON_EARLY_TERMINATION_MASK      (1 << 3)
+#define CSR_STOP_ON_ERROR_MASK                  (1 << 2)
+#define CSR_STOP_STATE_MASK                     (1 << 5)
+#define CSR_WRITE_FILL_LEVEL_MASK               0xFFFF0000
+#define CSR_WRITE_FILL_LEVEL_OFFSET             16
+
+#define START_DMA_FROM_FFT_MASK	( \
+		DESC_CTRL_GO_MASK | \
+		DESC_CTRL_END_ON_EOP_MASK)
+
+#define START_DMA_TO_FFT_MASK	( \
+		DESC_CTRL_GO_MASK | \
+		DESC_CTRL_GENERATE_SOP_MASK |\
+		DESC_CTRL_GENERATE_EOP_MASK)
+