blink.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

module blink(
	input rst_i,
	input clk_i,
	output reg led_o
);

parameter COUNTER_WIDTH = 32;
parameter OVERFLOW = 25_000_000;

reg[COUNTER_WIDTH-1:0] counter;

always @(posedge clk_i) begin
	if (rst_i) begin
		counter <= 0;
		led <= 1;
	end else if (counter == OVERFLOW-1) begin
		led_o <= ~led_o;
		counter <= 0;
	end else
		counter <= counter + 1;
end

endmodule