From 2b10511b25eec631d3b97867ba58b73ae56e4fa7 Mon Sep 17 00:00:00 2001 From: David Phillips Date: Tue, 18 May 2021 22:11:44 +1200 Subject: readme: Promote IP block headings --- README.md | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/README.md b/README.md index 9f751d8..69fde59 100644 --- a/README.md +++ b/README.md @@ -7,16 +7,14 @@ sessions on various aspects of Linux kernel driver development - it's not on any real boards, it's just a teaching tool. I do have a VHDL implementation which I will include once the IP blocks are more stable. -## IP blocks +Unless otherwise noted, for all reserved bits in registers, read as "don't +care" and write as 0. -Unless otherwise noted, for all reserved bits, read as "don't care" and write -as 0. - -### `cds9k-fan` +## IP Block: `cds9k-fan` FIXME add description -#### Register 0x0: FAN\_PWM +### Register 0x0: FAN\_PWM Mode: read-write @@ -32,7 +30,7 @@ The value for `duty_val` can be determined as: i.e. a linear scaling from 0-100% to 0x0-0xFF -#### Register 0x1: FAN\_TACH +### Register 0x1: FAN\_TACH Mode: read-only @@ -43,7 +41,7 @@ Read this register to determine the fan tachometer reading (FIXME units TBD). | Use | reserved | -### `cds9k-led` +## IP Block: `cds9k-led` The CDS9K LED control block allows PWM brightness control of a single LED (or LED die, in the case of multi-colour LEDs) as well as hardware-accelerated @@ -64,7 +62,7 @@ The `blink` signal has a fixed duty of 50% and a period programmable between 20 milliseconds and 5.1 seconds. The PWM signal has a fixed period of 40 microseconds (i.e. 25 kHz), and a duty programmable between 0 and 100%. -#### Register 0x0: LED\_PWM\_DUTY +### Register 0x0: LED\_PWM\_DUTY Mode: read-write @@ -80,7 +78,7 @@ The value for `duty_val` can be determined as: i.e. a linear scaling from 0-100% to 0x0-0xFF -#### Register 0x0: LED\_BLINK\_PERIOD +### Register 0x0: LED\_BLINK\_PERIOD Mode: read-write @@ -99,13 +97,13 @@ the PWM brightness programmed in the `LED_PWM_DUTY` register. | Use | reserved | period\_val | -### `cds9k-gpio` +## IP Block: `cds9k-gpio` The CDS9K GPIO block provides access to 16 basic I/O lines. Interrupts and pull-ups/pull-downs are not available. GPIO lines are individually selectable between input/hi-z and output. -#### Register: 0x0: PORT +### Register: 0x0: PORT Mode: read-write @@ -113,7 +111,7 @@ Mode: read-write | ---- | ------ | | Use | port | -#### Register: 0x1: DIRECTION +### Register: 0x1: DIRECTION Mode: read-write @@ -122,12 +120,12 @@ Mode: read-write | Use | direction\_mask | -### `cds9k-reset` +## IP Block: `cds9k-reset` The CDS9K reset control block exposes a single reset line which can be asserted and deasserted by writing different magic values to a single 16-bit register. -#### Register: 0x0: REG0 +### Register: 0x0: REG0 Mode: read-write @@ -137,7 +135,7 @@ Write as 0xDEAD to assert the reset, and write as 0x0000 to deassert the reset. | ---- | ------------ | | Use | reset\_magic | -#### Register: 0x1: RESERVED +### Register: 0x1: RESERVED Mode: read-only -- cgit v1.1